Intel(英特爾)的Alder Lake架構

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https://www.tomshardware.com/fea ... and-gracemont-cores


The Alder Lake SoC will span from desktop PCs to ultramobile devices with TDP ratings from 9W to 125W, all built on the Intel 7 process. The desktop PC comes with up to eight Performance (P) cores and eight Efficient (E) cores for a total of 16 cores and 24 threads and up to 30 MB of L3 cache for a single chip.

Intel's new hyper-threaded Performance (P) core, which comes with the Golden Cove microarchitecture designed for low-latency single-threaded performance, comes with an average of 19% more IPC than the Cypress Cove architecture in Rocket Lake. It also supports AVX-512 and AMX (a new AI-focused matrix-multiply ISA) for data center variants (both are disabled on consumer chips).

Intel's new single-threaded Efficiency (E) core, which comes with the Gracemont microarchitecture, is designed to improve multi-threaded performance and provide exceptional area efficiency (small footprint) and performance-per-watt. Four of these small cores fit in the same area as a Skylake core and deliver 80% more performance in threaded work (at the same power). A single E core also delivers 40% more performance than a single-threaded Skylake core (at the same power) in single-threaded work (caveats apply to both).

Intel's Thread Director is a hardware-based technology that provides enhanced telemetry data to the Windows 11 scheduler to assure that threads are assigned to either the P or E cores in an optimized manner, potentially easing one of the major pain points for a hybrid architecture in a standard desktop environment. This is the sleeper tech that enables the hybrid architecture.

Alder Lake does not support AVX-512 under any condition (fused off in P cores, not supported in E cores) to ensure an even ISA application.
Alder Lake supports either DDR4 or DDR5 (LP4x/LP5, too). Desktop PC supports x16 PCIe Gen 5 and x4 PCIe Gen 4, while mobile supports x12 PCIe Gen 4 and x16 PCIe Gen 3, Thunderbolt 4, and Wi-Fi 6E.

Intel will hold the inaugural Intel Innovation event October 27-28 with keynotes, demos and technical sessions. The event will be both in-person (location unannounced) and remote, and is largely thought to be the official unveiling of the Alder Lake processor stack.   

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Intel is on a similar trajectory with its collaboration with Microsoft to enable enhanced Windows 11 support for its x86 hybrid chips. In fact, Intel's Thread Director technology could be one of the most important aspects of the Alder Lake disclosures today. This is the sleeper tech that will determine Alder Lake's fate.

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Intel fully expects that Alder Lake will be more than the sum of its parts, with its hybrid x86 architecture delivering a non-linear performance increase. Intel has a seemingly great canvas to paint on with its pairing of efficient Gracemont and high-performance Golden Cove cores, but it has to make sure that the paint lands in the right place. Or, in this case, the threads land on the correct cores.

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If the threads land where they should, Intel could have a winner. In lightly threaded work, Gracemont purportedly provided 40% (or more) performance at the same power (ISO power) as the Skylake chip, meaning Skylake consumes 2.5 times more power to give the same level of performance as the Gracemont core. In threaded work, Gracemont delivers 80% more performance while consuming less power, or the same throughput at 80% less power. That means Skylake needs five times the power for the same performance, which is impressive indeed. Spam enough of these small cores into a package and you'll have a powerful chip that can trade blows with the heavyweights, even on the Arm side, but at equivalent or lower power.

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Things are just as impressive on the performance core side things. Intel claims Golden Cove delivers a 19% increase in IPC over Cypress Cove, which already is plenty impressive in single-threaded work. In fact, Golden Cove's IPC improvement is larger than the improvement from Skylake to Sunny/Cypress Cove. That's impressive, if true. Intel already leads in single-core performance, so Alder Lake could be well-positioned against AMD's Zen 4 chips if it can pull off a comparable advance.

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We won't have to wait much longer to see how effective Intel's preparations have been, Alder Lake comes to market in Fall 2021. We're sure to learn more at the inaugural Intel Innovation event October 27-28.

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Intel claims this jump is larger than the improvement from Skylake to Sunny Cove. That's impressive, if true. The second image in the album above comes from our lab results in our CPU Benchmark hierarchy. Intel's Rocket Lake Core i9-11900K, which has the Cypress Cove architecture that is very similar to Sunny Cove, currently leads the single-threaded performance hierarchy against AMD's chips. A quick glance at Intel's previous-gen Core i9-10900K shows that Intel's jump from Skylake to Sunny Cove represented a large improvement that helped it take the lead from AMD's Zen 3 architecture. That means Alder Lake's single-threaded performance could be well-positioned against AMD's Zen 4 chips if it can pull off a comparable advance.

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That's where Intel's Thread Director technology comes in. This hardware-based technology provides enhanced telemetry data to Windows 11 to assure that threads are scheduled to either the P or E cores in an optimized and intelligent manner, potentially easing one of the major pain points for a hybrid architecture in a standard desktop environment. It's also transparent to software.

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This technology works by feeding the Windows 11 operating system with low-level telemetry data that is collected from within the processor itself, thus informing the scheduler about the state of the core, be it power, thermal or otherwise. (As we'll cover shortly, Intel has integrated a new power microcontroller in each Gracemont core, a first, that collects similar data on the order of microseconds instead of milliseconds, so it might be part of the new telemetry system.)

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Additionally, Thread Director can also detect the instruction mix (scalar/vector) used in any given thread at a nanosecond granularity, and then communicate that data to the Windows 11 scheduler so the thread can be steered to the correct execution core, be that a high-performance P-Core or an efficient E-Core. Typically, vector/AI workloads will be prioritized to performance cores while scalar instructions and background tasks are moved to efficiency cores. However, the system is dynamic, so thread placement decisions can vary based on the mix of conditions and workloads present on the processor at any given time.